PLS computer field, high speed pulse output priority.
When there is a PTO/PWM output, the CPU passes the control terminals Q0.0 and Q0.1 to the PTO/PWM generator to disable the normal logic output.
The state of the output image register Q affects the start level of the PTO/PWM waveform. The state of Q0.0 and Q0.1 must be cleared before the high-speed pulse output.
The high-speed pulse output is suitable for the model. When outputting the high-frequency pulse signal, the transistor output type PLC should be selected.